Thesis Defence: All-Digital Transmitter Employing Delta-Sigma Modulation for S-Band Radio Applications
February 17 at 9:00 am - 1:00 pm
Edwin Firmansyah, supervised by Dr. Thomas Johnson, will defend their thesis titled “All-Digital Transmitter Employing Delta-Sigma Modulation for S-Band Radio Applications” in partial fulfillment of the requirements for the degree of Master of Applied Science in Electrical Engineering.
An abstract for Edwin Firmansyah’s thesis is included below.
Defences are open to all members of the campus community as well as the general public. Please email thomas.johnson@ubc.ca to receive the Zoom link for this defence.
Abstract
To meet the escalating demand for channel capacity in wireless communication systems, radio frequency (RF) beamforming has attracted significant interest. Using a bank of transmit RF chains to drive large-scale antenna arrays, these systems generate spatially adaptive radiation patterns that maximize spectral efficiency. The transition to massive array configurations necessitates highly scalable and power-efficient RF chains, which has led to all-digital transmitters (ADTs) emerging as a viable solution.
This thesis investigates the design and optimization of a field-programmable gate array (FPGA)-based ADT. Unlike conventional transmitters that rely on high-resolution Nyquist-rate digital-to-analog converters and upconversion, ADTs use delta-sigma modulation (DSM) to generate 1-bit signals that directly synthesize modulated RF carriers. DSM performs noise shaping on oversampled signals to encode high-resolution modulated RF carriers within a bandlimited region of a wideband spectrum. S-band operation is achieved using time-interleaved DSM, which parallelizes the DSM operations across multiple channels and serializes the outputs by exploiting an FPGA’s multi-gigabit serializers (MGS). This work examines trade-offs between channel count and clock rate which impacts the polyphase interpolation stage used for DSM oversampling, affecting both its attenuation profile and FPGA digital signal processing unit utilization. Additionally, enhanced polyphase interpolation with integrated fractional delay is proposed, improving wideband image rejection by up to 7 dB to mitigate inherent I/Q time-delay mismatches in ADTs.
Experimental results are presented to validate the proposed design methodology. In one configuration, a 4 GHz 64-QAM carrier at 32 MSym/s achieved an error-vector magnitude of 3% by driving the MGS at its maximum rate. In another configuration incorporating fractional delay, a 3.5 GHz QPSK carrier maintained greater than 40 dB image rejection ratio over an instantaneous bandwidth of 210MHz. Based on the analyzed trade-offs, this work offers recommendations for optimizing ADTs.
