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Doctoral Examination: DC-Fault Tolerant Multilevel Voltage Source Converters with Hybrid and Multiplexed-Arm Structures for High Voltage Direct Current Applications

January 26, 2023 at 9:00 am - 12:00 pm

Levi Bieber, supervised by Liwei Wang, will defend their dissertation titled “DC-Fault Tolerant Multilevel Voltage Source Converters with Hybrid and Multiplexed-Arm Structures for High Voltage Direct Current Applications” in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering.

An abstract for Levi’s dissertation is included below.

Examinations are open to all members of the campus community as well as the general public.

To register for this defence, please email the supervisor at liwei.wang@ubc.ca to obtain the zoom link.


Today’s state-of-the-art voltage-source-converter high-voltage direct-current (VSC-HVDC) technology uses modular-multilevel converters (MMCs) for their highly efficient AC/DC conversion and filterless operation. However, half-bridge submodule-based (HBSM) MMCs lack inherent DC-fault protection and require significantly more capacitive energy storage than the previous generation of converters, leading to converter stations of immense size and cost.

This dissertation proposes six novel VSC-HVDC-based technologies that amend the MMC’s disadvantages. Firstly, this dissertation presents three converter technologies: the Hybrid Three-Level Converter (H3LC), the Thyristor-based Hybrid Three-Level Converter (TH3LC), and the Hybrid Five-Level Converter (H5LC), which use AC-side cascaded submodules (SMs) and share a similar operating principle. Secondly, three converters that use DC-side cascaded SMs are proposed, including the Dual-Arm Converter (DAC), the Quad-Arm Converter (QAC), and the Multiplexed-Stack Converter (MSC), which require fewer SMs than the MMC by using proposed multiplexed converter arms (M-Arms). All the proposed converters have DC-fault protection enabled inherently – for the TH3LC, DAC, QAC, and MSC – or by novel DC-fault-blocking mechanisms in the cases of the H3LC and H5LC.

Results from HVDC-scale simulation studies are presented for all converters to demonstrate their proposed operating principles as well as to determine their expected semiconductor losses; meanwhile, lab-scale hardware verifications are presented for three converters. Analytical methods are proposed to programmatically calculate the converters’ theoretical energy storage requirements and semiconductor losses. Moreover, a CPU/FPGA co-simulation framework is presented that uses a proposed universal-equivalent model (UEM) for real-time simulation speeds.

The proposed converters all have reduced energy storage requirements compared to the MMC, with the H3LC requiring approximately one-tenth of the MMC’s energy storage. The TH3LC displays the highest efficiency of the proposed converters and has inherent DC-fault tolerance. The H5LC is demonstrated to have higher efficiency than the HBSM-MMC and the least number of SMs. The DAC uses only two M-Arms for AC/DC conversion and is inherently DC-fault tolerant. The QAC uses four SM-based stacks without DC-side capacitors. The MSC uses four SM-based stacks without DC-side capacitors and has DC-fault ride-through capability. The high efficiency and compactness of these converters are expected to facilitate their widespread acceptance throughout the industrial and academic communities.


January 26, 2023
9:00 am - 12:00 pm

Additional Info

Registration/RSVP Required
Yes (see event description)
Event Type
Thesis Defence
Research and Innovation, Science, Technology and Engineering
Alumni, Community, Faculty, Staff, Families, Partners and Industry, Students, Postdoctoral Fellows and Research Associates